The present invention is related to co-pending U.S. patent application Ser. No. 09/542,706 assigned to the assignee hereof, entitled, xe2x80x9cMETHOD AND DEVICE UTILIZING INVERSE SLOPE ISOLATION REGIONS IN A SEMICONDUCTOR DEVICE,xe2x80x9d filed on Apr. 5, 2000, and is hereby incorporated by reference.
1. Field of the Invention
The invention relates generally to semiconductor devices and more particularly to a method and apparatus for forming semiconductor devices utilizing a low temperature process.
2. Background of the Invention
As semiconductor device geometries continue to decrease, conventional silicon oxide gate dielectrics are reaching their limits. Smaller device geometries call for thinner gate dielectric layers in order to preserve the high capacitance that is desired for the gate structure. When silicon oxide is used as the gate dielectric material and very thin gate dielectric layers are desired, problems can arise due to leakage occurring through the very thin silicon oxide gate dielectric layer. As such, higher dielectric constant (higher-K) dielectric materials are being investigated for integration into current processing technology such that high capacitance can be achieved with thicker gate dielectric layers.
A problematic area in the utilization of new high-K dielectric materials arises at the interface between the high-K gate dielectric material and the underlying substrate. Small amounts of silicon oxide may form on the surface of the substrate prior to deposition of the high-K dielectric material. Subsequent annealing steps or other high temperature operations can cause migration of the various materials at this interface, which can lead to undesirable variations in the resulting structure at the interface. Attempts to integrate alternate gate dielectric materials utilize an underlying substrate that is crystalline silicon, and much effort has been expended to understand the additional process steps required to minimize aberrations when these alternate high-K dielectric materials are used in conjunction with underlying crystalline silicon substrates.
Another area of concern as semiconductor device geometries are scaled and developed is ensuring abrupt junctions for the various doped regions within semiconductor device structures. Abrupt junctions are desirable as they improve device-performance by reducing resistance along conductive paths associated with the doped regions.
In order to provide the abrupt junctions desired, specific modifications can be made to the implantation and annealing steps associated with formation of the source and drain regions in the semiconductor device structures. Specifically, variations on the implant operations include: reduction in the energy used, modification of the tilt angle of the implant, and the utilization of amorphous materials as the target for implantation. In terms of modifications to annealing operations, conventional furnace annealing has been replaced with rapid thermal annealing (RTA) operations that utilize much higher temperatures over a shorter time span to achieve the desired annealing operation. More recently these high temperature rapid thermal anneals have been replaced with lower temperature rapid thermal annealing operations such that amorphous substrate regions targeted for implantation can be recrystallized in a manner that minimizes diffusion of the dopants while activating the dopant materials within the crystalline structures that result.
When amorphous substrate materials are used as the targets for implantation steps and subsequently annealed to form the desired semiconductor device regions, end of range defects created at the interface between the amorphous substrate material and the underlying crystalline substrate material can produce undesirable defects in the resulting semiconductor structure. Such undesirable effects can include leakage that degrades device performance. Additional steps such as high temperature annealing can be used to remove or reduce the defects, but such high temperature annealing operations diffuse the dopant materials implanted earlier, thus degrading the abruptness of the junctions. Although low temperature annealing operations allow the abrupt junctions to remain, such low temperature annealing operations also leave the undesired end of range defects in place.